There are a wide variety of half bridge gate driver IC’s available. These offer high and low transistor gate driving functionality compressed into small packages to limit PCB size and complexity. Most of them require a bootstrap capacitor which means that they have limitations to the combined PWM frequency and duty cycle (due to capacitor charge time, leakage currents, gate currents, and drain currents). They also need to be reviewed for acceptable delay characteristics. However, they offer a cheap and fast solution for most systems that have fixed output or limited variable outputs.
Check out my improved gate driver circuit on hintsofozone.net.
This circuit can provide high efficiency gate switching for a wide range of input voltages.
In various switching power electronics, it is common to see four N channel enhancement mosfets connected in an H configuration with the load making the horizontal bridge and each mosfet making up half of the the long vertical sides.
There are a few issues with getting those high side mosfets to turn on. N channel enhancement mosfets become conductive when their gates are raised to a certain voltage above their sources. This is no problem for the low side FETs because their sources are connected to ground. So you just need to apply a 5-15V voltage with respect to ground and those FETS are on. But what happens if you try that with the high side? Well, once one of the low side FETs is on, the load gets pulled down to ground voltage on both sides. This lowers the source voltage on the high side FETs to a level where the 5-15V above ground is enough to turn it on. But there is a problem. If the high side FET turns all the way on like that, it’ll have such a small voltage drop from drain to source that the source voltage can be too high. About as high, in fact, as whatever the main high voltage is. And if this is higher than the 5-15V on the gate, that high side FET will start to turn off, but not necessarily all the way. It’ll stay on exactly enough to keep the source voltage low enough to stay as on as it is. This can easily burn up the transistor, depending on the load impedance. If the load impedance is 1 Ohm, and main voltage is 24VDC, the FET gate threshold is 3V, and the gate voltage is 10V, then the transistor needs to have enough impedance such that the voltage to the load is about 7V. Thus, the resistance of the transistor will set itself to around 3.4 Ohms. Trouble is, with that resistance at that voltage, the transistor has to dissipate 92.7 Watts which is enough to rapidly overheat and destroy any FET that doesn’t have some serious active cooling, and even if the FET can survive the heat, the load is still only getting 7V out of 24V, and only 38W of power. That’s no good.
One alternative is to use the high main voltage at the gate of the high side FET. In the last example, if you did this, the load would get closer to 21V, the FET still has to dissipate 63W, but the load gets a decent 442W. This is better, but it’s no where near as good as the FET can do.
The best method is to apply a voltage to the gate of the FET that is 5-15V higher than the high main voltage. This can be produced in a number of ways using switched devices, and if one is clever, and is driving the gates with a PWM wave, then one can use that switching to get the high side FET gate voltages up. The only problem with that is that if the duty cycle gets too close to 100%, then you end up right back in the second situation above, with massive heating of the high side FETs. A more flexible method would be to source the voltage for the gates from a separate boost converter with its own internal switching, but this is a more expensive choice.
Finally, there are a few P-channel power mosfets that can be driven a little easier, requiring only the high main voltage and a voltage 5-15V lower than that. This is problematic for two main reasons. Firstly, the timing is different. When using all of the same N channel FETs, you know they all have the same switching delays, with the P channels, you can expect different switching delays. Secondly, for the highest power electronics, P channel devices aren’t available (technically N channel FETs are also unavailable, but IGBT’s operate similarly to N Channel FETs).
I’ve updated 15A Simple and Hardy 24VDC Motor Controller significantly, for my use as a testing device (note the absence of external control inputs). It is isn’t cost or space optimized, but it will help me prove multiple concepts useful for a wide variety of power electronics.
Often, it is beneficial to pass PWM waves through driver circuits rather than applying the signal directly to the target. Each of these driver circuits is made up of components that have to switch off and on in order to repeat the original signal, and it takes a small amount of time for that switching to take place. Manufacturers will report how long these delays are, often separated into turn on and turn off times as they can be different. These manufacturer’s values can often be a range of delay times, and may be presented with minimum and maximum values. These ranges of delay times, and the differences between turn on and turn off times, can limit the maximum PWM frequency that can be effectively used with the circuit, and they determine the minimum useful duty cycle for a given frequency. On the plus side, for low power applications (less than 2000W) components can be found which have switching times in the tens of nanoseconds with nearly equal turn on and turn off delays, which means that PWM frequencies of less than a few hundred kHz are usually safe to use.
However, for components that can handle more power, two things increase with that capacity. First, the turn on and turn off times both increase in higher power rating components, and second, the turn on and turn off times get further apart, with the turn off times getting much larger than the turn on times. These characteristics necessarily limit maximum PWM frequencies, a fact which usually isn’t really a big problem because most power circuits output lower frequencies anyway. However, some power supplies need higher frequency switching, for instance, variable frequency drives that output SPWM. For these, one solution is to use multiple faster low power components in parallel. Doing this still adds delay, but with the right component selections, it can prevent the turn on delay and turn off delay from drifting apart which can permit the use of higher PWM frequencies.
In addition to the component delays, additional delays may occur due to PCB trace or wire geometry. When designing a circuit to distribute a PWM signal, it is beneficial to try to get all of the distances from the split point to the targets to be nearly the same, with the same trace thickness, and with nearly the same capacitance with respect to ground. This is important because the traces have switching delay times which depend upon their series resistance and shunt capacitance. Fortunately, the turn on/turn off delay times for traces are usually the same.
If you take a close look at my PIC based signal multiplier, it becomes apparent how easily that same design can be used for multiple DC analog (0-5)V signal manipulations, logic, and transforms. The chip consists of two protected DC analog (0-5)V signal inputs, and one PPTC protected DC analog output (0.4-4.6)V which is determined in the microprocessor programming by the duty cycle of the PWM output. Because the output is put through a power op-amp follower, the output signal has some decent power behind it. Thus, by modifying the PIC program, the device has a much wider range of possible uses that would otherwise require complicated and component intensive circuits to implement.
So the next time you’re thinking of building an analog circuit with 3+ opamps, you might consider this little guy, instead. You can contact me for a custom solution at https://hintsofozone.net/
I’ve been introduced to a painting process called Lumilor that can make any surface emit light. There are a lot of cool things that can be done with controllable glowing paint. The christmas lights applications alone are mind boggling.
This is the start of a more complicated PCB, The white lines represent connections that are required from the netlist generated from the schematic.
I got some software that I’d figured would be easier to run straight out of a windows operating system, rather than through an emulator, so I decided to try to rig up my debian machine with a windows dual boot. So I get the windows 10 iso and write it to a usb key to act as an install disk, something which I had done to install debian on this laptop in the first place. But now, it’s not working. I can’t get bios to find the usb efi file. I don’t want to go out and buy blank dvds, so I rigged up a virtual machine with VirtualBox in debian. On the first try I used a virtual hard disk (vhd) type of too large a fixed size. I didn’t have the space to have VBoxManage convert the thing to into raw format for dd onto the hard drive, and qemu-nbd doesn’t support vhd. So I gotta delete that image, start over with a vdi format virtual disk of a smaller size. This works alright, but for some reason my windows 10 iso isn’t working anymore, says it can’t find drivers. So I download a fresh windows 10 iso and get installed on the new smaller virtual disk. Hopefully, I’ll be able to dd it onto a spare partition I got, grub-update, and I’ll have a working dual boot machine, but if it won’t work, I’ll still have the VirtualBox in debian which can provide full windows experience at a reduced speed.
Alas, the boot configuration files from the VirtualBox vdi won’t work on the hard drive, and editing them is problematic. It can probably be done with the right grub drive mapping and chainloading, but a promising alternative is to use grub loopback to mount the windows 10 iso straight from a location on the hard drive, which I have this evening found to work very well for linux install disks but getting the windows disk to work with ntldr or chainloader remains illusive. In the meantime, there’s always the option of just burning a dvd, but in the meantime I can still work in the virtual windows machine.